| 摘要 |
A data sensing timing modulating circuit, particularly for non-volatile memories. The circuit includes means for generating a first voltage (V=f(Icell)) that is a function of the conductivity of a memory cell and of a second substantially constant reference voltage (V=Vref), a first delay circuit, and a second delay circuit supplied by the first and second voltages. The first delay circuit modulates, as a function of the first voltage, the start time of the switching of an equalization signal that is normally present in the memory device. The switching of this signal indicates the beginning of a data sensing step. The second delay circuit modulates the slope of the switching of the equalization signal, as a function of the first voltage, so as to determine the instant when the equalization signal ends the switching to start the subsequent data sensing step.
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