| 摘要 |
PROBLEM TO BE SOLVED: To efficiently execute an arithmetic processing at high speed through the use of few hardware by inputting the outputs of shifters, which are not simultaneously used, to any adder through an OR gate. SOLUTION: Shifter groups 1-12 shifting input data by prescribed bits and adder groups 31-35 adding the outputs with combination designated by a multiplication coefficient are provided. When multiplication is executed by using all the existing multiplication coefficients, the number of adders, which is required for the addition processing, is arranged on the output side of the respective shifters at the time of adding the outputs of the maximum number of the shifters if the prescribed multiplication coefficient is used. When multiplication is executed by using all the existing multiplication coefficients, the combination of the shifters whose outputs are not simultaneously used is selected and the outputs of the shifters are inputted to any adder through the OR gate. The multiplier using the number of adders, which is sufficiently smaller than the number of bits of the multiplication coefficient, can be realized. |
