发明名称 Ausführungsvorrichtung für bedingte Verzweigungsbefehle
摘要 An electronic computer according to this invention is capable of executing a plurality of instructions simultaneously. It is characterized by comprising a flag adding section for judging whether or not each of a plurality of instruction is either a delayed branch instruction or a squash branch instruction, and based on the results, adding a flag indicating an abort condition to each instruction, and a command execute abort section for aborting execution of each instruction on the basis of whether or not the flag added to each instruction to indicate the abort condition and each branch instruction hold true. <IMAGE>
申请公布号 DE69130757(D1) 申请公布日期 1999.02.25
申请号 DE1991630757 申请日期 1991.11.29
申请人 KABUSHIKI KAISHA TOSHIBA, KAWASAKI, KANAGAWA, JP 发明人 MINAGAWA, KENJI, C/O INTELL. PROPERTY DIV., MINATO-KU, TOKYO 105, JP;AIKAWA, TAKESHI, C/O INTELL. PROPERTY DIV., MINATO-KU, TOKYO 105, JP;SAITO, MITSUO, C/O INTELL. PROPERTY DIV., MINATO-KU, TOKYO 105, JP
分类号 G06F9/38;G06F12/10;(IPC1-7):G06F9/38;G06F13/42 主分类号 G06F9/38
代理机构 代理人
主权项
地址
您可能感兴趣的专利