NOISE REDUCTION CIRCUITS

摘要

A noise reduction circuit useful as a clock restoration circuit includes a DC removal circuit (67) for removing a DC level from an input pulse train. An integrator (54) integrates the input pulse train after a DC level has been removed and a comparator (59) compares the integrator output with a threshold value (Vmp) to detect for a missing pulse. A pulse generator (65) inserts into the input pulse train an additional pulse delayed with respect to any missing pulse and an output pulse train having reduced noise is derived from the integrator output. In another noise reduction circuit blanking pulses B* are generated and are used to cancel additional spurious pulses in the input pulse train. A phase noise reduction circuit producing a pulse train having a predetermined phase relationship and/or duty cycle relative to an input signal or a clock signal is also described. Also described is the application of such circuits to a fractional rate multiplier circuit and a fractional-N phase-locked loop synthesiser.