发明名称 |
Digital signal processor |
摘要 |
To provide a signal processor for performing processing in fewer cycles by selecting one of the two different operations in accordance with a flag signal and performing the selected operation without the use of a conditional branch instruction, the signal processor is provided with an instruction decoder, a control selecting circuit, a selecting circuit and an arithmetic unit. The instruction decoder decodes an instruction to output two control signals. The control selecting circuit is connected to the instruction decoder and selects one of the control signals in accordance with a flag signal stored in a flag holding circuit to output the selected signal. The selecting circuit selects one of a plurality of input data in accordance with the control signal outputted by the control selecting circuit and outputs the selected data. The arithmetic unit performs an operation on the data outputted by the selecting circuit. <IMAGE> |
申请公布号 |
EP0825528(A3) |
申请公布日期 |
1998.12.23 |
申请号 |
EP19970114599 |
申请日期 |
1997.08.22 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
MIYAKE, JIRO;URANO, MIKI;INOUE, GENICHIRO |
分类号 |
G06F9/305;G06F9/30;G06F9/318 |
主分类号 |
G06F9/305 |
代理机构 |
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地址 |
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