SEMICONDUCTOR MEMORY DEVICE

摘要

PROBLEM TO BE SOLVED: To shorten the reading time of a ROM, and enable the high speed reading. SOLUTION: Bit line pairs respectively consisting of main bit line 5 and sub-bit line 6 are provided. 1st and 2nd ROM memory cells 1a and 1b in which different sets of information are stored are respectively composed of main and sub-memory cell transistors 2 and 3. Latching circuits 7 which are composed respectively of two inverters 8 and 9 connected in reverse-parallel with each other are provided between the main and sub-bit lines 5 and 6 to read the sets of information stored in the ROM memory cells 1a and 1b. In the respective memory cells 1a and 1b, the sets of information on the main and sub-bit lines 5 and 6 which are connected to the main and sub-memory cell transistors 2 and 3 are determined and the sets of information reversed by the latching circuits 7 are held on the main and sub-bit lines 5 and 6 which are not connected to the main and sub-memory cell transistors 2 and 3, so that the information on the bit lines can be determined without the precharge of the bit lines and the reading time can be shortened.