| 摘要 |
A process for fabricating a vertical structure high carrier mobility transistor on a substrate (1) of crystalline silicon doped with impurities of the N type, having a collector region (2) located at a lower portion of the substrate, the process comprising the steps of: defining a window (10) in the semiconductor substrate (1); providing a first implantation of germanium (Ge) atoms through said window (10); providing a second implantation of acceptor dopants through said window (10) to define a base region; applying an RTA treatment, or treatment in an oven, to reconstruct the crystal lattice within the semiconductor substrate comprising a silicon/germanium alloy (Si1-xGex); forming a first thin dielectric layer (12) of silicon dioxide (SiO2) by chemical vapor deposition; depositing a second dielectric layer (14) onto said first dielectric layer (12); depositing a polysilicon layer (15) onto said second dielectric layer (14); etching away, within the window region (10), said first (12) and second (14) dielectric layers, and the polysilicon layer (15), to expose the base region (3) and form isolation spacers (50) at the window edges; forming an N-doped emitter (4) in the base (3) and window regions. This fabrication process is specially attentive to the formation of the silicon dioxide SiO2/GexSi1-x interface present in vertical structure HBT transistors, if isolation spacers are to be formed. The fabrication process of this invention allows the frequency field of application of HBT transistors to be further extended, while eliminating deviations of the base currents from the ideal. <IMAGE> |
