发明名称 Testable circuit with reduced pin count
摘要 <p>The smart card has a single input/output pin (I/O) to allow the microcontroller (12) to communicate with the outside. Interface registers (16) between a peripheral device (14) and the microcontroller can be connected as a shift register forming a test exploration path that is accessible by serial communication, timed by the clock signal applied to the clock pin of the peripheral. A test assistance circuit (18) initiates the connection of the registers in the test configuration when a test bit accessible through the I/O line is validated and the I/O pin is forced from the outside to a state different to its default state.</p>
申请公布号 EP0875830(A1) 申请公布日期 1998.11.04
申请号 EP19980410043 申请日期 1998.04.28
申请人 STMICROELECTRONICS S.A. 发明人 PRUNIER, JACQUES
分类号 G06F11/36;(IPC1-7):G06F11/00 主分类号 G06F11/36
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