| 摘要 |
PROBLEM TO BE SOLVED: To provide a floating point processor with which floating point data are operated while reducing the number of logic stages by reducing processing required for handling non-normalized numbers. SOLUTION: An h-bit generation circuit 36 is provided for generating the integer part of floating point data, and the generated integer part and the accuracy information of instruction from an instruction decoder 3 are held in a register file 11 together with arithmetic data. An arithmetic processing part 1 operates the arithmetic data held in the register file 11 and writes the result in the register file 11. Besides, the accuracy information of instruction is held in the register file 11 as well. Further, a correction circuit 5 is provided for correcting the exponent part of non-normalized number. |
