Voltage reference generator for EPROM memory array

摘要

A technique is disclosed for reading a memory element of an EPROM array embedded in a microcontroller chip which has been scaled down from a previous design by virtue of reduced line widths of a process technology used for fabricating the chip. The microcontroller chip has a predetermined supply voltage, and the array comprises rows and columns of addressable memory elements which may be selectively accessed to read data content therefrom in a low voltage mode in which the supply voltage initially rises and ultimately reaches substantially its maximum voltage during a read cycle. A regulated reference voltage is used to exercise row and column control in the low voltage read mode by tracking the level of the supply voltage up to a certain preselected level below the maximum supply voltage, and by clamping the row and column control voltage at substantially the preselected level despite increases in the level of the supply voltage above the preselected level.