发明名称 Digital power management system
摘要 A digital power management system for an analog-to-digital converter operates to cause the sample rate of the analog-to-digital converter to function at an original desired frequency so long as changing input signals are present. Whenever activity at the input of the analog-to-digital converter ceases to change, the system automatically decreases the clock signal sampling rate to a slower clock frequency, or shuts down the application of clock signals. This conserves power until a change in the analog input is detected, whereupon the system automatically increases the sample clock frequency back to the original frequency.
申请公布号 US5784051(A) 申请公布日期 1998.07.21
申请号 US19970788847 申请日期 1997.01.27
申请人 VLSI TECHNOLOGY, INC. 发明人 HARROW, SCOTT E.;NALUBOLA, RISHI
分类号 G06F1/32;G06F3/033;G06F3/038;G06F3/05;(IPC1-7):G09G5/08 主分类号 G06F1/32
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