| 摘要 |
A clock signal generator for an IC tester has a clock control circuit provided between a jitter reduction circuit and an IC device to be tested. The clock control circuit inhibit the clock signal from reaching the IC device for a time period required for a clock signal changes to a new frequency. The clock signal generator includes: a timing generator for generating clock signals and timing signals based on a test program, a pattern generator which receives the timing signals from the timing generator for producing test pattern signals to be supplied to the IC device based on the test program, a jitter reduction circuit for receiving a clock signal from the timing generator and for reducing a jitter of the clock signal, and a clock control circuit for inhibiting the clock signal from the jitter reduction circuit from being supplied to the IC device for a inhibit period determined by the test program when a frequency of the clock signal has been changed. |
