| 摘要 |
<p>A path transistor logical circuit is composed by making a dichotomizing deciding graph from a logical function and mapping its each node to a path transistor selector of two input-one output-one control input, so as to make a logical circuit excellent in circuit feature such as area, delay time and power consumption by combining the path transistor logical circuit with a CMOS logical circuit. In the path transistor logical circuit, a path transistor selector, which is operating as NAND logic or NOR logic, with one of the two inputs excluding a control signal input fixed to logical constant 1 or 0, is replaced with the CMOS gate of a logically equivalent NAND, NOR or the like, and if the value of the specified circuit feature is closer to an optimum (for example, area, delay time, power consumption, or the like is smaller) in the case of being replaced with the CMOS gate than otherwise, the path transistor selector is replaced with the CMOS gate.</p> |
