| 摘要 |
A controller (CTMI) for multiple transfer of data organized by a microprocessor (MPU) between a plurality of memories (SRAM, VRAM) and a computer bus (PSB), including a plurality of registers (REGI, REGO) programmed by the microprocessor for writing into them of information enabling the organization of the transfer over a first and a second channel. The controller includes a central bus (BC, BC1) connected to each of the registers; a first and a second channel controller, associated with the first and second channel, respectively; and an arbitration device connected on the one hand to the second interface and on the other to each of the channel controllers. The arbitration device allocates a given channel to the data routes going to the memories or the microprocessor. The channel controllers control, for each channel, the writing access of the microprocessor to the registers associated with that channel and the transfer of data to each of the memories.
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