| 摘要 |
<p>The apparatus includes a phase locked loop having a loop bandwidth, comprising a digital signal processor. A digitally controlled frequency source generates a second signal having a second frequency based on a reference clock and the output of the digital signal processor. A phase detector receives a first signal and the second signals and generates a phase difference signal proportional to the phase difference between first and second frequencies. The phase difference signal has a first frequency component representing the phase difference which lies above the loop bandwidth of the phase locked loop. An A/D converter digitizes the phase difference signal and generates phase difference signal data having the first frequency components. The digital signal processor produces a second frequency components by processing the phase difference signal data. The second frequency components represent the phase difference which lies below the loop bandwidth of the phase locked loop. The digital signal processor outputs a frequency control data to the digitally controlled frequency source such that the first and second frequencies are in phase locked condition. The phase difference signal data from the A/D converter and the processed phase difference signal data from the digital signal processor are combined by a signal data combining unit. A measurement unit measures the phase difference between the first and second phase signals.</p> |
