| 摘要 |
A memory access chip set includes a data buffer chip and a system controller chip. The data buffer chip contains storage elements that buffer data values transferred between a memory and either the host data bus or the peripheral bus. In one aspect, the storage elements are transparent latches, and not master/slave flip-flops. In another aspect, the storage elements are operated asynchronously. In another aspect, the storage elements are exactly two levels deep (additional accommodations are made in the case of data busses having mismatched widths). The arrangement of storage elements is such that only a single control pin is required on the data buffer chip to enable them, and only a single input pin (plus, in some cases, a clock input pin) for externally coordinating outputs from the storage elements for synchronous transfer over the destination bus. The system controller chip generates both the input control signal for the data buffer chip and CAS# for the memory, such that propagation delay variations in the system controller chip for the input control signal are substantially similar those in the system controller chip for CAS#.
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