发明名称 |
Synchronization circuit for ATM cells |
摘要 |
A synchronization circuit for ATM cells transferred in an ATM communication system, wherein the synchronization circuit receives and holds in a bit serial manner the input bit trains constituting the received ATM cells by a shift register unit, performs a CRC operation in a bit serial manner on the held input bit trains by a continuous CRC arithmetic unit in accordance with a simplified CRC operation process different from the usual CRC operation process, and performs the necessary synchronization control upon receiving the CRC arithmetic operation result at a synchronization control unit, thereby enabling CRC arithmetic operations to be performed continuously and by simple hardware on the headers in the ATM cells. <IMAGE> |
申请公布号 |
EP0448074(B1) |
申请公布日期 |
1998.06.10 |
申请号 |
EP19910104331 |
申请日期 |
1991.03.20 |
申请人 |
FUJITSU LIMITED |
发明人 |
HYODO, RYUJI;NISHINO, TETSUO;ISONO, OSAMU;TACHIBANA, TETSUO;MIYAMOTO, NAOYUKI;OOMURO, KATSUMI;YONETA, TSUYOSHI |
分类号 |
G06F11/10;H03M13/00;H04L7/00;H04L7/04;H04L7/08;H04L12/70;H04Q11/04 |
主分类号 |
G06F11/10 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|