| 摘要 |
An improved graphics processor is of the type having a graphics engine and a graphics FIFO buffer in communication with the graphics engine. The buffer is also in communication with a host processor over a bus so as to provide request code and data from the host processor to the graphics engine. The improvement in a preferred embodiment utilizes a plurality of logical FIFOs, including a normal FIFO and a protected FIFO, having addresses all mapping to the same physical graphics FIFO buffer. User access via an application is provided only to the normal FIFO, whereas system level code is provided access to all of the logical FIFOs, so that the protected FIFO can be used for control of the graphics processor. In a further embodiment, a logical sync FIFO is employed also. The sync FIFO is used in error recovery to receive and store a request that can be detected by the graphics engine as a cue to restart normal processing. Related methods are also provided.
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