High speed instruction alignment unit for aligning variable byte-length instructions according to predecode information in a superscalar microprocessor

摘要

An instruction alignment unit is provided which transfers a fixed number of instructions from an instruction cache to each of a plurality of decode units. The instructions are selected from a quantity of bytes according to a predecode tag generated by a predecode unit. The predecode tag includes start-byte bits that indicate which bytes within the quantity of bytes are the first byte of an instruction. The instruction alignment unit independently scans a plurality of groups of instruction bytes, selecting start bytes and a plurality of contiguous bytes for each of a plurality of issue positions. Initially, the instruction alignment unit selects a group of issue positions for each of the plurality of groups of instructions. The instruction alignment unit then shifts and merges the independently produced issue positions to produce a final set of issue positions for transfer to a plurality of decode units./!