发明名称 Heterogeneous symmetric multi-processing system
摘要 In a heterogenous symmetric multi-processing system, processors from distinct families of processors are integrated on a single platform. The processors are coupled to an implementation specific communication mechanism through family specific bus interface converters. Shared memory and I/O subsystems may be coupled to the implementation specific communication mechanism as well. An operating system maintains separate ready queues for each family of processors. Each ready queue is responsible for scheduling execution of process threads on its associated family of processors. The operating systems facilitates execution of both single mode binary code files and mixed mode binary code files. When a thread is created, the operating system determines the initial processor family to associate with the thread based on the binary code stream that the thread will begin executing. The thread is placed in the ready queue of that family. As the thread executes it may require services from another family of processors in order to natively execute the next set of instructions in the binary code file. When services are required, the operating system reschedules those instructions on a processor which executes those instructions natively. Means are provided to return the thread to a processor in the previous family of processors in order to support mixed mode instruction stream subroutine support.
申请公布号 AU5087398(A) 申请公布日期 1998.05.22
申请号 AU19980050873 申请日期 1997.10.27
申请人 UNISYS CORPORATION 发明人 DUANE J. MCCRORY
分类号 G06F9/318;G06F9/48;G06F9/50 主分类号 G06F9/318
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