| 摘要 |
<p>PROBLEM TO BE SOLVED: To make a wide lock range compatible with less phase jitter with a simple configuration by processing extraction of a data coding time with a specific circuit configuration. SOLUTION: An interface circuit 4 at a data transmitter side separates a transmission timing from transmission data from a terminal 14 and gives the timing to an edge detection circuit 6. The edge detection circuit 6 is provided with a series circuit of a plurality of D flip-flop circuits driven by a clock signal from an oscillator 5, detects leading and trailing of a transmission timing in 4-bit width and provides an edge detection bit string of 'HLHL' and 'HLLH' to a code rule error insert circuit 2 according to the detection. The code rule error insert circuit 2 encodes the bit string by assigning 'code rule error' to the 'H' of the edge detection bit and 'no code rule error' to the 'L$' of the edge detection bit and inserts the result to the coded transmission data and provides an output of the result to a transmission circuit 1. A clock signal of the oscillator 5 is set to a sufficiently high constant frequency.</p> |
