| 摘要 |
<p>PROBLEM TO BE SOLVED: To consider, in case clock distribution using a multi-pin clock driver is performed, 'clock skew distributed from the same pin is smaller than clock skew distributed from a different pin' and to reduce the time and man-hours needed to generate and correct a hardware description. SOLUTION: A logic synthesis means 2 generates a before-clock-distribution circuit according to the hardware description in a hardware description storage means 1. A clock net connection information storage means 4 stores clock net connection information indicating the style of clock distribution at the use of the multi-pin clock driver. A clock distributing means 5 generates an after-clock-distribution circuit (logic circuit wherein clock pins of all clock driving elements are connected by a net from one of circuit clock pin) according to the before-clock-distribution circuit and clock net connection information.</p> |
