发明名称
摘要 PURPOSE:To convert binary numbers corresponding to two registers into a decimal number by clearing off the leading bits of binary values, dividing the cut binary value is 10M to decompose the binary value corresponding to one register, converting the decomposed binary value into a decimal value, and then combining the converted decimal values. CONSTITUTION:The leading part bit of a binary number to be converted is cleared off by a clearing part and the cleared binary number is divided by 10M through a dividing part 20 to find out a quotient W1 and a remainder W2. Since the leading bit of the binary number is cleared off, the values W1, W2 can be stored in one register. In a 1st processing stage, the value W1, W2 are converted into decimal values W'1, W'2 by a decimal processing part 40 and W'3 = W'1 X 10M + W'2 is calculated to obtain the decimal number W'3. In a 2nd processing part, the decimal number corresponding to the bit cleared off by the clearing part is added to the value W'3, so that binary numbers corresponding to two registers can be converted into a decimal number.
申请公布号 JP2723319(B2) 申请公布日期 1998.03.09
申请号 JP19890316989 申请日期 1989.12.06
申请人 FUJITSU KK 发明人 TERADA TAKANORI
分类号 G06F5/00;(IPC1-7):G06F5/00 主分类号 G06F5/00
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