发明名称
摘要 <p>PURPOSE:To smoothly stop an internal clock and the operation of an internal circuit at arbitrary timing even in the case of an external clock or the internally generated clock without newly providing any external terminal. CONSTITUTION:A stop signal generating circuit 1 is provided to generate a stop signal STOP for turning the levels of signals to an active level when the signals of first and second terminals TX1 and TX2 for oscillator are turned to a low level. The stop signal STOP is supplied to the internal circuit and corresponding to the active level of this stop signal STOP, an oscillation circuit 2 is turned to an inactive state.</p>
申请公布号 JP2722920(B2) 申请公布日期 1998.03.09
申请号 JP19920051180 申请日期 1992.03.10
申请人 NIPPON DENKI KK 发明人 MYATA SHINJI
分类号 G06F1/04;(IPC1-7):G06F1/04 主分类号 G06F1/04
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