Method and apparatus for executing single beat write store instructions during a cache store linefill operation

摘要

A method and apparatus for executing a single beat write (SBW) store instruction during a cache store linefill operation are disclosed. In accordance with the present disclosure, an address associated with the cache memory store linefill operation is first received. This address comprises a tag portion and an index portion. For the cache store linefill operation, the tag portion of this address is sent to a tag latch while the index portion is sent to a burst index latch. During the cache store linefill operation, a second address associated with the single beat write store instruction is received. This second address also comprises a tag portion and an index portion. In response to a determination that a critical word of the cache memory store linefill has been received, the tag portion of the second address is sent to the tag latch and the index portion of the second address is sent to an SBW index latch. By doing so, the single beat write store instruction may be executed before the completion of the cache store linefill operation.