TIMING ANALYZING METHOD IN CIRCUIT DESIGNING,申请号JP19960206260-传众专利搜索

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发明名称	TIMING ANALYZING METHOD IN CIRCUIT DESIGNING
摘要
申请公布号	JPH1049556(A)	申请公布日期	1998.02.20
申请号	JP19960206260	申请日期	1996.08.05
申请人	SANYO ELECTRIC CO LTD	发明人	KUROKAWA ATSUSHI
分类号	G06F17/50;(IPC1-7):G06F17/50	主分类号	G06F17/50
代理机构		代理人
主权项
地址

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