Clock generating circuit for digital circuit operating in synchronism with clock, semiconductor integrated circuit including them, and logical gate used for them

摘要

An oscillation stop signal holding latch 3 which stores a value deciding significant/unsignificant of an oscillation stop signal 4, and a NOR gate 21 which controls, when the oscillation stop signal 4 is significant, to stop the generation of a clock signal 7 and controls, when a predetermined signal is inputted from an input terminal 1 of an external signal in the abovementioned states with the oscillation stop signal being unsignificant, to resume the generation of the clock signal 7, and further a sampling circuit 10 between the input terminal 1 of the external signal and the oscillation stop signal holding latch 3 are provided. And a gate circuit 30 which forcibly makes the oscillation stop signal 4 become unsignificant so as to generate the clock signal 7 when the input signal from the input terminal 1 of the external signal is significant is provided. This enables the sampling circuit 10 to sample the input signal from the input terminal 1 of the external signal.