| 摘要 |
Disclosed is a circuit to separate a brightness signal and a chroma signal in a processor for digital image signal. The circuit in a vertical relative processor comprises the first zero detector, the second zero detector and a comparision value generator. The first zero detector detects whether n(n is interger) bits of stream data are zero in the output from the first switch. The second zero detector detects whether n(n is interger) bits of stream data are zero in the output from the second switch. The comparision value generator generates a comparision input data according to the first and second zero detector. Thereby, the input signal to the vertical relative processor can be actively switched, the error output can be reduced, and a remained brightness signal which is generated from no vertical relativeness can be eliminated.
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