发明名称 MULTI-LEVEL INVERTER
摘要 PROBLEM TO BE SOLVED: To provide a multi-level inverter that can suppress snubber loss properly and has at least four-level output using a clamp snubber circuit. SOLUTION: DC input terminals are indicated by 1A-1D, an AC output terminal is indicated by 2, positive-side inverse continuity switches are indicated by 3A-3C, and negative-side continuity switches are indicated by 4A-4D. By fuming on or off each continuity switch, the AC output terminal 2 can generate a four-level potential that is equivalent to the potential of four DC input terminals. The maximum application voltage of each inverse continuity switch can be clamped by the maximum terminal voltage of each corresponding clamp snubber capacitor, thus suppressing surge voltage and reducing the loss of a snubber circuit.
申请公布号 JPH09322547(A) 申请公布日期 1997.12.12
申请号 JP19960139798 申请日期 1996.06.03
申请人 TOSHIBA CORP 发明人 SATO SHINJI
分类号 H02M1/00;H02M7/48;H02M7/483 主分类号 H02M1/00
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