发明名称 |
ELECTRONIC CIRCUIT AND MANUFACTURE THEREOF |
摘要 |
<p>PROBLEM TO BE SOLVED: To avoid reduction of the coverage by elongating a second opening to a region outside a first wiring so that a cover insulation film does not appear on the inner wall of the second opening at an outer region of the first wiring to avoid forming a recess into the inner wall of the region. SOLUTION: An anodic oxide film 35b exposed at the bottom of contact holes C3 is removed by wet etching. In the section where the inner wall of the contact hole C3 is located on an inner region of a gate line 34b, the film 35b is side-etched. As the result, a recess 40 is formed into a lower part of the inner wall of the hole C3. In the section where the inner wall of the contact hole C3 is located outside the gate line 34b, the anodic oxide film on the surface of the gate wiring 34b is entirely removed to expose part of a gate insulation film 33b and part of a base SiO2 film 31 at both sides of the gate line 34b.</p> |
申请公布号 |
JPH09306990(A) |
申请公布日期 |
1997.11.28 |
申请号 |
JP19960119304 |
申请日期 |
1996.05.14 |
申请人 |
FUJITSU LTD |
发明人 |
OHORI TATSUYA;HORI TETSUO |
分类号 |
G02F1/1343;G02F1/136;G02F1/1362;G02F1/1368;H01L21/306;H01L21/336;H01L21/768;H01L21/8234;H01L23/498;H01L23/522;H01L23/538;H01L27/088;H01L29/786;(IPC1-7):H01L21/768;G02F1/134;H01L21/823 |
主分类号 |
G02F1/1343 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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