| 摘要 |
<p>A semiconductor memory module comprises a main addressable memory (102) responsive to first and second timing signals to activate a selected memory cells therein and a substitute addressable memory (108) containing memory cells which are substitutable for faulty cells in the main memory (102). A controller (106) responsive to a received timing signal or received timing signals from a host computer (100) generates modified timing signals to accommodate tolerance variations in the substitute memory.</p> |
