发明名称 PAD LAYOUT STRUCTURE OF SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To eliminate a bottleneck such as a shortage of pins in number in a semiconductor device by a method wherein a pad is added to each of all the buffers of a prescribed integrated circuit. SOLUTION: Regions 13 are arranged between an inner circuit region 1 and buffers 31, 32, 33,..., wherein one of the regions 13 is large enough in space for providing a second pad 71. First pads 5a1 and 5b1 arranged in zigzag are provided to the chip peripheral edges of the buffers 31, 32, 33,.... The first pads 5a1 and 5b1 are connected to the buffers 31 and 32 with inter-pad/buffer wirings 41 and 42. The second pad 71 is arranged between the buffer 34 which is not connected to the pads 5a1 and 5b1 and the inner circuit region 1, and connected to the buffer 34 with an inter-pad/buffer wiring 44, whereby all the buffers mounted on a chip can be set usable, so that a shortage of pins in number can be resolved.
申请公布号 JPH09293747(A) 申请公布日期 1997.11.11
申请号 JP19960105216 申请日期 1996.04.25
申请人 NEC YAMAGATA LTD 发明人 INAMURA TADAYUKI
分类号 H01L21/60;(IPC1-7):H01L21/60 主分类号 H01L21/60
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