发明名称 DESIGNING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a designing method in which data is not broken down due to increase of wiring, increase in signal delay and a clock skew when a scan chain connection is performed. SOLUTION: In a designing method for a semiconductor integrated circuit, a pair of scan registers which perform a scan chain connection are selected (SA4). Then, the straight-line distance on hardware between respective output terminals of scan registers at a previous stage and scan data input terminals of scan registers at a later stage is computed (SA5). In addition, on the basis of a computed result, the output terminal of the scan register at the previous stage, in which the straight-line distance becomes minimum, is selected (SA6), and the connection of the selected output terminal to the scan data input terminal of the scan register at the later stage is decided (SA7). Then, in every pair of scan registers, a scan chain connection is performed by using the decided output terminal (SA8).
申请公布号 JPH09288152(A) 申请公布日期 1997.11.04
申请号 JP19970000111 申请日期 1997.01.06
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 TAKEOKA SADAMI;ICHINOMIYA TAKAHIRO;MOTOHARA AKIRA
分类号 G01R31/28;G06F11/22;G06F17/50;H01L21/82;H01L21/822;H01L27/04 主分类号 G01R31/28
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