发明名称 Semiconductor device having planarized wiring
摘要 A first contact hole and a second contact hole are formed in an insulating film on the surface of a substrate, and thereafter a blanket tungsten (W) layer is deposited on the substrate surface, with or without a barrier metal layer being interposed therebetween. The first contact hole has a small size +E,uns a+EE so that the W layer can fully bury the first contact hole, whereas the second contact hole has a large size +E,uns b+EE over +E,uns a+EE size +E,uns c+EE where a<c<b so that a desired wiring layer coverage ratio is attained. The deposited W layer is etched back while leaving the W layer in the first contact hole and a tapered W layer in the second contact hole. A wiring layer such as Al alloy is deposited on the substrate surface. The unnecessary wiring layer and barrier metal layer are patterned to form a wiring pattern. Wiring layers having a good burying state and a good coverage state can be obtained. A yield of manufacturing wiring layers can be improved.
申请公布号 US5679981(A) 申请公布日期 1997.10.21
申请号 US19960633543 申请日期 1996.04.17
申请人 YAMAHA CORPORATION 发明人 KUWAJIMA, TETSUYA
分类号 H01L21/3205;H01L21/768;H01L23/522;(IPC1-7):H01L23/48;H01L23/52 主分类号 H01L21/3205
代理机构 代理人
主权项
地址