发明名称 DEETASHORISOCHI
摘要 PURPOSE:To reduce the number of signal lines, by installing a register set capable of reading and writing data arbitrarily on each LSI, in a data processor in which plural processing units operating independently are constituted of the LSIs, etc., respectively. CONSTITUTION:In a write operation, the prescribed field of an instruction register 18 is set simultaneously at register setting and addressing registers 19 and 20, at the time of starting an instruction, and in execution of the instruction, similarly, a register address is set simultaneously at the register setting and addressing registers 19 and 20 by a microinstruction, through a data bus 3. The data of a register 13 is transferred from a signal line 11 to the data bus 3, and it is written at the corresponding register of a register set 4 through a signal line 6 in the LSI1, and it is written at the corresponding register of a register set 5 through a signal line 7 in the LSI2.
申请公布号 JP2657947(B2) 申请公布日期 1997.09.30
申请号 JP19860186667 申请日期 1986.08.08
申请人 HITACHI SEISAKUSHO KK 发明人 HIRAMATSU MASATAKA
分类号 G06F7/00;G06F9/38 主分类号 G06F7/00
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