| 摘要 |
PROBLEM TO BE SOLVED: To perform planarization by selectively arranging an insulating film in a low-altitude portion of a substrate having a step. SOLUTION: A memory array portion in which a stack capacitor 409 is formed has an altitude approximately 0.5μm higher than that of a lower portion (peripheral circuit portion). After an SOG film portion applied on a semiconductor substrate main surface having a relatively low is exposed to light to form an exposed SOG film 417, an unexposed portion is removed using an alkaline solution. A via-hole is formed in a desired part of an SOG film 418 and then a metal wiring 419 is formed, thus providing a multilayer wiring structure. In this case, since the semiconductor substrate main surface on which the SOG film 418 is formed is substantially planarized in the memory array portion and the peripheral circuit portion, easy formation of a pattern at an M1 wiring spacing of 1μm pitch is enabled. |
