Digital phase locked loop with a digital voltage controlled oscillator in a recording information reproducing apparatus

摘要

A digital PLL circuit in a recording information reproducing apparatus, wherein a sampled value is obtained by A/D converting a read signal read from a recording medium at a sampling timing according to a reproduction clock signal, a phase error occurring in the read signal is detected on the basis of the sampled value, an oscillation data signal sequence whose data value increases or decreases at a changing period corresponding to the phase error is generated, the oscillation data signal sequence is converted to an analog signal, an oscillation signal is formed, and a signal obtained by converting the oscillation signal to a square wave is set to a reproduction clock signal for sampling.