| 摘要 |
A digital circuit for generating a signal with a pulse width that is other than a half multiple of the clock is shown. The signal width can be greater or less than the clock period. This digital circuit includes a signal modifier, responsive to the clock signal, for generating a signal with a logic 0 state in response to the first clock edge and a signal with a logic 1 state in response to a toggle signal. A delay circuit generates the toggle signal in response to the second clock edge and a time delay measured from the second clock edge. With the appropriate delay element in the delay circuit, the generating of the toggle signal can be selectively delayed to extend the duration of the pulse.
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