| 摘要 |
PROBLEM TO BE SOLVED: To provide a detection circuit for PLL lock showing that two clock signals to be compared are mutually in-phase even when their frequencies are different. SOLUTION: A CLK A and a CLK B are respectively inputted through front edge detectors 16 and 18 to a coincidence detector 22, and the case of simultaneously generating front edges is shown. This output is counted by a 16-bit counter 24. The outputs of this counter 24 and a 16-bit counter 26 for inputting the CLK A are inputted to a coincidence detection circuit 32, and the repetition of continuous clock edges is shown. The output of the coincidence detector 32 is compared with the output of a 32-bit counter 34 for inputting the CLK A through the next coincidence detector 38. When coincidence is detected, that output is inputted to a latch 42, and the phase lock of CLK A and CLK B is shown. The 16-bit counter 24, 32-bit counter 34 and latch 42 are respectively reset every time of prescribed counting.
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