| 摘要 |
<p>PROBLEM TO BE SOLVED: To improve plotting performance and to make possible retreating and moving the data without lowering the plotting performance. SOLUTION: This storage is provided with first and second low-order side transfer gates TGa1, TGa2 and low-order side data registers DRa1, DRa2, and high-order transfer gates TGb1, TGb2 and high-order data registers DRb1, DRb2 respectively answering to column addresses of the low-order side and the high-order side of a memory cell array part 1. The storage is provided with a serial address control part 23 and a tile map control part 24 performing data transfer between with the memory cell array part 1 by one side loworder side and high-order side transfer gates (e.g. TGa1, TGb1) and data registers (DRa1, DRb1) among the first and second transfer gates and registers, and controlling so as to perform input/output of the data with an external circuit and controlling a binary boundary jump function.</p> |
