| 摘要 |
A current limting circuit in which, when the input d.c. voltage (UE) is raised from zero volt to the reference voltage (Usoll) by the connected load (RL, CL), an output d.c. voltage (IA), flows only when the value of the input d.c. voltage (UE) rises to a value above a low voltage threshold (Uu) which is below the reference voltage (Usoll). |
