The memory cells each include a single electron transistor and a single electron storage element. The transistor is controlled by the charge stored in the memory element. when a read voltage is present, a current dependent on the stored charge flows through the single electron transistor without changing the stored charge. When a greater write voltage is present, the stored charge is changed. The memory cells are switched between two sets of lines which cross each other in a memory cell arrangement. The memory element includes at least a tunnel element connected to a first line via a tunnel contact and to a memory node via a second tunnel contact. The node is capacitively controlled by a gate electrode.
