| 摘要 |
It is an object to reduce circuit scale and increase operation speed of a memory test circuit which performs a memory test according to the ping-pong pattern. An address signal of a remarked cell is generated by an LFSR (76) and address signals for other cells are generated by an LFSR (75). The LFSR (76) updates the generated address signal every time the LFSR (75) generates one cycle of address signals. The address signals of the LFSR's (75, 76) are alternately switched by a selector circuit (78) and outputted to a RAM (2A).
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