| 摘要 |
A high-speed programmable macrocell includes structure sufficient to implement a combined in the combinatorial storage signal path when the macrocell is operated in the combinatorial, and storage modes of operation. The macrocell includes, a master circuit (including a polarity multiplexer), and a slave circuit (including a transmission gate). The polarity multiplexer is responsive to input data for generating an output signal corresponding to one of a true and complemented state of the input data, according to a polarity configuration bit. The master circuit stores the multiplexer output in response to a low-to-high transition of a clock signal when operating in the storage mode. The master circuit, when in the combinatorial mode, will always pass the multiplexer output therethrough. The transmission gate is coupled to the master circuit and, in the storage mode, will block the output of the master circuit from passage therethrough when the clock is low, but will pass such output therethrough when the clock is high. The transmission gate will always pass the master circuit output when operating in the combinatorial mode. The slave circuit generates output data having true and complemented states in both the storage and combinatorial modes. When in the combinatorial mode, the slave circuit, which, in addition to the transmission gate includes an inverter and a tristate buffer connected in a feedback arrangement, stores and outputs data when the clock is low, based on the data provided to it when the clock is high.
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