Integrated oscillator circuit

摘要

The circuit includes an oscillator stage and a PLL driving stage for producing the oscillator signal and controlling the phase locked loop (PLL). Both stages are formed from two npn transistors (Q1,Q2) in parallel and with their emitters connected together at a node (K1) to which a DC source (SQ1) is also connected for supplying the transistors. The oscillating circuit (SK) includes a capacitor (C1) and coil (L1) which are intended for turning the oscillator signal to the desired frequency (10.7 MHz) along a line (AL1). The collector terminal of the second transistor is connected to the PLL pin (AP2) and a second line (AL2) in order to generate an alternating voltage for the PLL. The sum of the AC (I1,I2) is constant but their phase difference is 180 degrees.