发明名称 |
Synchronous semiconductor memory device having a mode requiring an internal clock signal and a mode not requiring the internal clock signal |
摘要 |
A refresh control circuit of a DLL circuit responds to an auto refresh detection signal AR and a self refresh detection signal SR to inhibit input of clock signals ECLK and RCLK to a phase comparator and to a voltage control delay circuit. The DLL circuit can be stopped in a mode where an internal clock signal is not required to reduce power consumption.
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申请公布号 |
US5629897(A) |
申请公布日期 |
1997.05.13 |
申请号 |
US19950524927 |
申请日期 |
1995.09.08 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
IWAMOTO, HISASHI;KONISHI, YASUHIRO |
分类号 |
G11C11/407;G11C7/10;G11C7/22;G11C11/401;G11C11/403;G11C11/406;(IPC1-7):G11C8/00 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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