| 摘要 |
The programmable logic device (PLD) of this invention includes two or more programmable logic blocks interconnected by a programmable switch matrix that includes a programmable input switch matrix and a programmable centralized switch matrix. Each programmable logic block is coupled to a plurality of programmable I/O macrocells by an output switch matrix. Each programmable I/O macrocell is connected to one of a plurality of I/O pins for the programmable logic block. In one embodiment, an input macrocell couples an I/O macrocell and the associated I/O pin to the programmable input switch matrix. The programmable input switch matrix provides a uniform treatment of all feedback signals to the programmable centralized switch matrix and thereby simplifies signal routing, provides an improved functionality balance, and improved resource utilization within the PLD. The output switch matrix routes output signals from a programmable logic block to any one of a multiplicity of the I/O macrocells. The output switch matrix and the input switch matrix decouple the programmable logic block and centralized switch matrix from the pin-out and the feedback architecture of the PLD. Thus, the output switch matrix and the input switch matrix may be effectively used with a wide variety of programmable interconnect structures and programmable logic block architectures to achieve enhanced resource utilization, routability and functionality.
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