| 摘要 |
<p>1,097,085. Digital computers. INTERNATIONAL BUSINESS MACHINES CORPORATION. Nov. 11, 1965 [Dec. 23, 1964], No. 47848/65. Heading G4A. A parallel arithmetic unit comprises a pair of multi-order operand registers 12, 14, Fig. 8, arranged with interconnecting logical circuitry, Figs. 1-7 (not shown) which when responding to cyclically generated ADD or SUBTRACT control signals from pulse drivers 74 or 75 stores the " half-add " or " half-subtract " sum in one register 12 and the " carries " or " borrows " in the other register 14. OR gate 20 receiving inputs as a result of any non-zero digits in the " carries " register 14 inhibits further generation of the control signals and thereby suppresses advance of the data processor to the next sub-step. The separate crcuits for each operation are described with reference to Figs. 1-7 (not shown) whereby the outputs from the various stages provide or control set or reset inputs to the like order stages and the higher carry/borrow stages. The operations described are ADD; SUBTRACT (without complementing); SHIFT LEFT (as carries resulting from partial subtraction from zero); OR; EXCLUSIVE OR and EXCHANGE (between registers 12, 14). Sense amplifiers 72 provide means for loading the registers. The parallel arithmetic is performed by momentary control signals on the parallel registers 12, 14 which are interconnected by logic circuits. In Fig. 1 (not shown) the interconnections comprise AND and OR gates (16), (18) but in the other circuits such as Fig. 2 the binary triggers have set and/or reset D.C. output lines energized by coincident energization of both D.C. and A.C. set and reset input lines.</p> |
