发明名称 IMAGE DATA TREATMENT TIME REDUCTION CIRCUIT
摘要 A image data process time decreasing circuit for facsimile in order to decrease the spending time where is a time to store the compressed image data with the memory. The said apparatus consist of a address decoder outputting the chip selection signal and the image chip selection signal, a data processor outputting the compression/restoration image data depending on the chip selection signal, a address latch means where transmit the address to the memory, a data buffer input/output the data to the data processor, a memory storing the image data, a bidirectional buffer, a address bus latch, a periphery gate.
申请公布号 KR970003411(B1) 申请公布日期 1997.03.18
申请号 KR19930031395 申请日期 1993.12.30
申请人 LG ELECTRONICS CO.,LTD. 发明人 NAM, CHA-HEE
分类号 H04N1/00;(IPC1-7):H04N1/00 主分类号 H04N1/00
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