| 摘要 |
PROBLEM TO BE SOLVED: To shorten signal propagation delay time and reduce layout area, in a semiconductor device or a semiconductor storage device. SOLUTION: A pair of power supply sublines vdd, vss composed of second layer wirings E2a, E2b are stretched parallel in the Y direction in such a manner that the sublines branch vertically from specified positions [E2, E3] of main power supply lines Vdd Vss composed of third layer wirings E3c, E3d stretching in the X direction. In a region 10 surrounded by the power supply sublines vdd, vss, each of the transistors (TRP1 , TRN1 ), (TRP1 , TRN1 ) of CMOS inverters IV1 , IV2 is arranged in a specified direction. Third layer wirings E3a, E3b constituting gloval signal lines GL0, GL1 intersect (pass) the upper part of the power supply sublines vdd, vss and an active area (transistor region) from the outside of the region 10, and stretch in the X direction as far as a connection point [E1, E2, E]. |
